Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN

Jitesh Poojary; S. Ramprasath; Sachin S. Sapatnekar; Ramesh Harjani

doi:10.1109/rfic54547.2023.10186141

Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN

Jitesh Poojary
, S. Ramprasath
, Sachin S. Sapatnekar
, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

The extended manual layout process for RF and analog/mixed-signal design restricts design space exploration and limits design productivity. This work demonstrates the efficacy of an automated layout generator versus a manual approach using a state-of-the-art MIMO receiver. Multiple smaller floorplans of the layout are generated automatically in hours compared to weeks for a single manual layout. Measured results from an automatically generated layout fabricated in TSMC 65nm CMOS show performance numbers comparable to the manual design. Measured in-band/in-notch IIP3 and out-of-band/in-notch IIP3 are 18.3dBm and 23.64dBm, respectively.

Original language	English (US)
Title of host publication	2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023
Editors	Jennifer Kitchen, Steven Turner
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	57-60
Number of pages	4
ISBN (Electronic)	9798350321227
DOIs	https://doi.org/10.1109/rfic54547.2023.10186141
State	Published - 2023
Event	2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023 - San Diego, United States Duration: Jun 11 2023 → Jun 13 2023

Publication series

Name	2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Conference

Conference	2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023
Country/Territory	United States
City	San Diego
Period	6/11/23 → 6/13/23

Bibliographical note

Funding Information:
ACKNOWLEDGEMENTS This work was supported in part by the DARPA IDEA program (contract N660011824048).

Publisher Copyright:
© 2023 IEEE.

Keywords

Automated RF-AMS layout synthesis
Design productivity
Design space exploration
MIMO receiver

Publisher link

10.1109/rfic54547.2023.10186141

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Poojary, J., Ramprasath, S., Sapatnekar, S. S., & Harjani, R. (2023). Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN. In J. Kitchen, & S. Turner (Eds.), 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023 (pp. 57-60). (2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/rfic54547.2023.10186141

Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN. / Poojary, Jitesh; Ramprasath, S.; Sapatnekar, Sachin S. et al.
2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. ed. / Jennifer Kitchen; Steven Turner. Institute of Electrical and Electronics Engineers Inc., 2023. p. 57-60 (2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Poojary, J, Ramprasath, S, Sapatnekar, SS & Harjani, R 2023, Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN. in J Kitchen & S Turner (eds), 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Institute of Electrical and Electronics Engineers Inc., pp. 57-60, 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023, San Diego, United States, 6/11/23. https://doi.org/10.1109/rfic54547.2023.10186141

Poojary J, Ramprasath S, Sapatnekar SS , Harjani R. Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN. In Kitchen J, Turner S, editors, 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 57-60. (2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)). doi: 10.1109/rfic54547.2023.10186141

Poojary, Jitesh ; Ramprasath, S. ; Sapatnekar, Sachin S. et al. / Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN. 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023. editor / Jennifer Kitchen ; Steven Turner. Institute of Electrical and Electronics Engineers Inc., 2023. pp. 57-60 (2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)).

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abstract = "The extended manual layout process for RF and analog/mixed-signal design restricts design space exploration and limits design productivity. This work demonstrates the efficacy of an automated layout generator versus a manual approach using a state-of-the-art MIMO receiver. Multiple smaller floorplans of the layout are generated automatically in hours compared to weeks for a single manual layout. Measured results from an automatically generated layout fabricated in TSMC 65nm CMOS show performance numbers comparable to the manual design. Measured in-band/in-notch IIP3 and out-of-band/in-notch IIP3 are 18.3dBm and 23.64dBm, respectively.",

keywords = "Automated RF-AMS layout synthesis, Design productivity, Design space exploration, MIMO receiver",

author = "Jitesh Poojary and S. Ramprasath and Sapatnekar, \{Sachin S.\} and Ramesh Harjani",

note = "Funding Information: ACKNOWLEDGEMENTS This work was supported in part by the DARPA IDEA program (contract N660011824048). Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2023 ; Conference date: 11-06-2023 Through 13-06-2023",

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AB - The extended manual layout process for RF and analog/mixed-signal design restricts design space exploration and limits design productivity. This work demonstrates the efficacy of an automated layout generator versus a manual approach using a state-of-the-art MIMO receiver. Multiple smaller floorplans of the layout are generated automatically in hours compared to weeks for a single manual layout. Measured results from an automatically generated layout fabricated in TSMC 65nm CMOS show performance numbers comparable to the manual design. Measured in-band/in-notch IIP3 and out-of-band/in-notch IIP3 are 18.3dBm and 23.64dBm, respectively.

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Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN

Abstract

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