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Exploiting timing error resilience in processor architecture
John Sartori
, Rakesh Kumar
Electrical and Computer Engineering
Research output
:
Contribution to journal
›
Article
›
peer-review
7
Scopus citations
Overview
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Dive into the research topics of 'Exploiting timing error resilience in processor architecture'. Together they form a unique fingerprint.
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Keyphrases
Timing Speculation
100%
Processor Architecture
100%
Timing Error Resilience
100%
Error Rate
80%
Architecture Optimization
60%
Energy Saving
20%
Efficiency Increase
20%
Increased Yield
20%
Design Practice
20%
Nondeterminism
20%
Additional Energy
20%
Razor
20%
Moore's Law
20%
Worst-case Design
20%
Nonincreasing
20%
Error Resilience
20%
Guard Band
20%
CMOS Design
20%
Resilience Mechanisms
20%
Popular
20%
Overscaling
20%
Computer Science
Processor Architectures
100%
Error Resilience
100%
Design Practice
50%
Moore's Law
50%
Popular Approach
50%