Exploiting the prefetching effect provided by executing mispredicted load instructions

Resit Sendag, David J Lilja, Steven R. Kunkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. This wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor.

Original languageEnglish (US)
Title of host publicationEuro-Par 2002 Parallel Processing - 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002 Proceedings
EditorsBurkhard Monien, Rainer Feldmann
PublisherSpringer Verlag
Number of pages13
ISBN (Print)3540440496
StatePublished - 2002
Event8th International Euro-Par Conference on Parallel Processing, Euro-Par 2002 - Paderborn, Germany
Duration: Aug 27 2002Aug 30 2002

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other8th International Euro-Par Conference on Parallel Processing, Euro-Par 2002

Bibliographical note

Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2002.


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