Exploiting basic block value locality with block reuse

Jian Huang, David J. Lilja

Research output: Contribution to conferencePaper

60 Scopus citations

Abstract

Value prediction at the instruction level has been introduced to allow more aggressive speculation and reuse than previous techniques. We investigate the input and output values of basic blocks and find that these values can be quite regular and predictable, suggesting that using compiler support to extend value prediction and reuse to a coarser granularity may have substantial performance benefits. For the SPEC benchmark programs evaluated, 90% of the basic blocks have fewer than 4 register inputs, 5 live register outputs, 4 memory inputs and 2 memory outputs. About 16% to 41% of all the basic blocks are simply repeating earlier calculations when the programs are compiled with the -O2 optimization level in the GCC compiler. We evaluate the potential benefit of basic block reuse using a novel mechanism called a block history buffer. This mechanism records input and live output values of basic blocks to provide value prediction and reuse at the basic block level. Simulation results show that using a reasonably-sized block history buffer to provide basic block reuse in a 4-way issue superscalar processor can improve execution time for the tested SPEC programs by 1% to 14% with an overall average of 9%.

Original languageEnglish (US)
Pages106-114
Number of pages9
StatePublished - 1999
EventProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA - Orlando, FL, USA
Duration: Jan 9 1999Jan 13 1999

Other

OtherProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA
CityOrlando, FL, USA
Period1/9/991/13/99

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    Huang, J., & Lilja, D. J. (1999). Exploiting basic block value locality with block reuse. 106-114. Paper presented at Proceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA, Orlando, FL, USA, .