Exploiting algorithmic noise tolerance for scalable on-chip voltage regulation

Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selcuk Kose

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

With the advent of on-chip digital low-dropout (DLDO) regulators, distributed on-chip voltage regulation has become increasingly promising. Environmental and operating conditions have been demonstrated to degrade DLDO performance, which directly affects execution accuracy. The area overhead (OH) needed to compensate aging-induced voltage noise degradation can be significant. Accordingly, in this paper, the algorithmic noise tolerance of certain processor components is exploited as an area-quality control knob to trade the program output quality for area OH. Furthermore, efficient and lightweight techniques utilizing a unidirectional shift register and reduced clock pulsewidth triggering are proposed to realize a novel aging-aware (AA) DLDO to achieve a better area and quality tradeoff. Owing to the large number and distributed nature of voltage regulators, with the proposed design, both the number of regulators utilized in the system and the size of each local regulator are scalable to satisfy the needs of different applications and processor components with varying algorithmic noise tolerance. It is demonstrated through simulation of an IBM POWER8 like processor that the proposed AA design can achieve up to, respectively, 43.2% and 3 × transient and steady-state performance improvement. Additionally, more than 10% area OH saving can be achieved over a 5-year period.

Original languageEnglish (US)
Article number8528543
Pages (from-to)229-242
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number1
DOIs
StatePublished - Jan 2019

Bibliographical note

Funding Information:
Manuscript received April 11, 2018; revised July 19, 2018; accepted August 27, 2018. Date of publication November 9, 2018; date of current version December 28, 2018. This work was supported in part by the National Science Foundation CAREER Award under Grant CCF-1350451, in part by the National Science Foundation Award under Grant CCF-1421988, and in part by the Cisco Research Award. (Corresponding author: Longfei Wang.) L. Wang and S. Köse are with the Department of Electrical Engineering, University of South Florida, Tampa, FL 33620 USA (e-mail: longfei@mail.usf.edu; kose@usf.edu).

Keywords

  • Algorithmic noise tolerance
  • digital low-dropout (DLDO) regulator
  • reliability
  • scalable on-chip voltage regulation
  • voltage noise

Fingerprint Dive into the research topics of 'Exploiting algorithmic noise tolerance for scalable on-chip voltage regulation'. Together they form a unique fingerprint.

Cite this