Exhaustive scheduling and retiming of digital signal processing systems

Tracy C. Denk, Keshab K. Parhi

Research output: Contribution to journalArticle

24 Scopus citations

Abstract

Scheduling and retiming are important techniques used in the design of hardware and software implementations of digital signal processing algorithms. In this paper, techniques are developed for generating all scheduling and retiming solutions for a strongly connected data-flow graph, allowing a designer to explore the space of possible implementations. Formulations are developed for two scheduling problems. The first scheduling problem assumes a bit-parallel target architecture. The formulation for this problem is general because it considers retiming the data-flow graph as part of scheduling, and this formulation reduces to the retiming formulation as a special case. The second scheduling problem assumes a bit-serial target architecture. Based on these formulations, the conditions for a legal scheduling solution are derived, and a systematic technique is presented for exhaustively generating all legal scheduling solutions for a strongly connected data-flow graph. Since retiming is a special case of scheduling, this systematic technique can also be used for exhaustively generating all legal retiming solutions. A technique is also developed for exhaustively generating only those bit-parallel schedules which satisfy a given set of resource constraints. The techniques for exhaustively generating scheduling and retiming solutions are demonstrated for several filters. For example, we show that a simple filter such as the biquad has 224 possible retiming solutions for a latency of one time unit. We also show that a fifth-order wave digital elliptic filter has 4.7 million and 580 million scheduling solutions for iteration periods of 17 and 18, respectively.

Original languageEnglish (US)
Pages (from-to)821-838
Number of pages18
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume45
Issue number7
DOIs
StatePublished - Dec 1 1998

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Keywords

  • Data flow graphs
  • High-level synthesis
  • Parallel architectures
  • Retiming
  • Scheduling
  • Signal processing
  • Very large scale integration

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