Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems

Veni Mohan, Akhilesh Iyer, John Sartori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Ultra-low-power (ULP) chipsets are in higher demand than ever due to the proliferation of ULP embedded systems to support growing applications like the Internet of Things (IoT), wearables and sensor networks. Since ULP systems are also cost constrained, they tend to employ general purpose processors (GPPs) rather than more energy-efficient ASICs, even though they typically run a single application for the lifetime of the system. Prior work showed that it is possible to reduce the operating voltage and thus the power of such systems without reducing the frequency, since the fixed software stack of a system typically only exercises a subset of a processor's paths, and unexercised paths need not meet timing constraints for the system to work correctly. In this context, we find additional scope for power reduction by intelligently optimizing the processor design based on the system's application-specific activity characteristics to allow an even lower safe operating voltage. We demonstrate automated techniques that maximize the applicationspecific voltage reduction for a system, resulting in 35% additional power savings, on average, compared to the application-specific minimum voltage before optimization and 48% total power savings compared to the original design at nominal voltage.

Original languageEnglish (US)
Title of host publicationProceedings of the 55th Annual Design Automation Conference, DAC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781450357005
DOIs
StatePublished - Jun 24 2018
Event55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: Jun 24 2018Jun 29 2018

Publication series

NameProceedings - Design Automation Conference
VolumePart F137710
ISSN (Print)0738-100X

Other

Other55th Annual Design Automation Conference, DAC 2018
CountryUnited States
CitySan Francisco
Period6/24/186/29/18

    Fingerprint

Keywords

  • Dynamic timing slack
  • Embedded systems
  • Internet of-things
  • Ultra-low-power

Cite this

Mohan, V., Iyer, A., & Sartori, J. (2018). Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 [a42] (Proceedings - Design Automation Conference; Vol. Part F137710). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3196046