For general synchronous circuits, input and output data are stored in latches or flip-flops which are triggered by the clock signal, so the clock period is a measurement of circuit performance. Previous studies on this issue are restricted by the assumption of triggering all inputs at the same cIock phase. We propose a new method to reduce the clock period without the above assumption. The proposed method allows the existence of clock skew and produces a better clock period. The improvement in circuit performance is demonstrated by our experimental results.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 1998|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: May 31 1998 → Jun 3 1998