Enhancing circuit performance under a multiple-phase clocking scheme

Yaun chung Hsu, Shangzhi Sun, David H.C. Du, Xuedao Chu

Research output: Contribution to journalConference article

2 Scopus citations

Abstract

For general synchronous circuits, input and output data are stored in latches or flip-flops which are triggered by the clock signal, so the clock period is a measurement of circuit performance. Previous studies on this issue are restricted by the assumption of triggering all inputs at the same cIock phase. We propose a new method to reduce the clock period without the above assumption. The proposed method allows the existence of clock skew and produces a better clock period. The improvement in circuit performance is demonstrated by our experimental results.

Original languageEnglish (US)
Pages (from-to)219-222
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume6
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: May 31 1998Jun 3 1998

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