Enhancing beneficial jitter using phase-shifted clock distribution

Dong Jiao; Jie Gu; Pulkit Jain; Chris H. Kim

doi:10.1145/1393921.1393932

Enhancing beneficial jitter using phase-shifted clock distribution

Dong Jiao
, Jie Gu
, Pulkit Jain
, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.

Original language	English (US)
Title of host publication	ISLPED'08
Subtitle of host publication	Proceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages	21-26
Number of pages	6
DOIs	https://doi.org/10.1145/1393921.1393932
State	Published - 2008
Event	ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India Duration: Aug 11 2008 → Aug 13 2008

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
Country/Territory	India
City	Bangalore
Period	8/11/08 → 8/13/08

Keywords

Clock jitter
Resonant supply noise

Publisher link

10.1145/1393921.1393932

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Enhancing beneficial jitter using phase-shifted clock distribution. / Jiao, Dong; Gu, Jie; Jain, Pulkit et al.
ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. 2008. p. 21-26 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jiao, D, Gu, J, Jain, P & Kim, CH 2008, Enhancing beneficial jitter using phase-shifted clock distribution. in ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 21-26, ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, India, 8/11/08. https://doi.org/10.1145/1393921.1393932

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title = "Enhancing beneficial jitter using phase-shifted clock distribution",

abstract = "Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the {"}beneficial jitter{"} effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15\% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.",

keywords = "Clock jitter, Resonant supply noise",

author = "Dong Jiao and Jie Gu and Pulkit Jain and Kim, \{Chris H.\}",

year = "2008",

doi = "10.1145/1393921.1393932",

language = "English (US)",

isbn = "9781605581095",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

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AU - Kim, Chris H.

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Y1 - 2008

N2 - Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.

AB - Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.

KW - Clock jitter

KW - Resonant supply noise

UR - https://www.scopus.com/pages/publications/57549087226

UR - https://www.scopus.com/pages/publications/57549087226#tab=citedBy

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DO - 10.1145/1393921.1393932

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SN - 9781605581095

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

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BT - ISLPED'08

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ER -

Enhancing beneficial jitter using phase-shifted clock distribution

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Keywords

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