An n-well CMOS technology has been developed for high-speed/precision 10-V analog operation while retaining VLSI packaging densities and performance. Several enhancements to a fully scaled 1. 2- mu m CMOS process were made to attain performance levels necessary for state-of-the-art data-conversion applications. The technology incorporates components essential for analog circuit design such as high-gain/low-noise n-p-n BJTs, laser trimmable Cr-Si resistors, and extremely accurate interpoly oxide capacitors. Inclusion of an optimized LDD structure on n-channel transistors has permitted 10-V CMOS capabilities down to 2. 5- mu m drawn gate lengths.