ENHANCED FULLY-SCALED 1. 2 mu M CMOS PROCESS FOR ANALOG APPLICATIONS.

R. K. Reich, C. Rahn, M. Holt, J. W. Schrankler, D. H. Ju, G. D. Kirchner

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

A high performance analog technology has been developed for an enhanced 1. 2- mu m VLSI digital CMOS process. Enhancements made in order to attain 10-V analog capabilities included a vertical NPN bipolar transistor, Cr-Si resistors, interpoly oxide capacitors, and an LDD structure on n-channel transistors. Extensive characterization and evaluation of the enhancements are presented which demonstrate the potential of this process for fabricating large-scale data conversion and signal processing circuits. Circuit performance of the digital CMOS has been well preserved with virtually no degradation.

Original languageEnglish (US)
Pages (from-to)192-195
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Dec 1 1985

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