Energy efficient signaling in DSM CMOS technology

Imed Ben Dhaou; Hannu Tenhunen; Vijay Sundararajan; Keshab K. Parhi

doi:10.1109/iscas.2001.922072

Energy efficient signaling in DSM CMOS technology

Imed Ben Dhaou
, Hannu Tenhunen
, Vijay Sundararajan
, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

The problem of efficient signaling over on-chip interconnect in DSM technology is addressed. A signaling scheme based on low-swing combined with repeater insertion and resizing is derived for both cascaded inverters and inverter chains. The proposed scheme has been implemented in 0.25 μm 2.5 V, 6 metal layers CMOS process. HSPICE results showed that our scheme leads to a substantial energy-saving ratio without speed degradation.

Original language	English (US)
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Publisher	IEEE Computer Society
Pages	411-414
Number of pages	4
ISBN (Print)	0780366859, 9780780366855
DOIs	https://doi.org/10.1109/iscas.2001.922072
State	Published - 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: May 6 2001 → May 9 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	5

Other

Other	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	5/6/01 → 5/9/01

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/iscas.2001.922072

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Dhaou, I. B., Tenhunen, H., Sundararajan, V., & Parhi, K. K. (2001). Energy efficient signaling in DSM CMOS technology. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 411-414). Article 922072 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 5). IEEE Computer Society. https://doi.org/10.1109/iscas.2001.922072

Energy efficient signaling in DSM CMOS technology. / Dhaou, Imed Ben; Tenhunen, Hannu; Sundararajan, Vijay et al.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, 2001. p. 411-414 922072 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 5).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dhaou, IB, Tenhunen, H, Sundararajan, V & Parhi, KK 2001, Energy efficient signaling in DSM CMOS technology. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922072, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 5, IEEE Computer Society, pp. 411-414, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 5/6/01. https://doi.org/10.1109/iscas.2001.922072

Dhaou IB, Tenhunen H, Sundararajan V, Parhi KK. Energy efficient signaling in DSM CMOS technology. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society. 2001. p. 411-414. 922072. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings). doi: 10.1109/iscas.2001.922072

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AB - The problem of efficient signaling over on-chip interconnect in DSM technology is addressed. A signaling scheme based on low-swing combined with repeater insertion and resizing is derived for both cascaded inverters and inverter chains. The proposed scheme has been implemented in 0.25 μm 2.5 V, 6 metal layers CMOS process. HSPICE results showed that our scheme leads to a substantial energy-saving ratio without speed degradation.

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ER -

Energy efficient signaling in DSM CMOS technology

Abstract

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