Energy efficient signaling in deep submicron CMOS technology

Imed Ben Dhaou; Vijay Sundararajan; Hannu Tenhunen; Keshab K Parhi

doi:10.1109/ISQED.2001.915250

Energy efficient signaling in deep submicron CMOS technology

Imed Ben Dhaou, Vijay Sundararajan, Hannu Tenhunen, Keshab K Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25pm, 2.5V, 6 metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001
Publisher	IEEE Computer Society
Pages	319-324
Number of pages	6
ISBN (Electronic)	0769510256
DOIs	https://doi.org/10.1109/ISQED.2001.915250
State	Published - 2001
Event	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 - San Jose, United States Duration: Mar 26 2001 → Mar 28 2001

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2001-January
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001
Country/Territory	United States
City	San Jose
Period	3/26/01 → 3/28/01

Bibliographical note

Publisher Copyright:
© 2001 IEEE.

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISQED.2001.915250

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Dhaou, I. B., Sundararajan, V., Tenhunen, H., & Parhi, K. K. (2001). Energy efficient signaling in deep submicron CMOS technology. In Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001 (pp. 319-324). Article 915250 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January). IEEE Computer Society. https://doi.org/10.1109/ISQED.2001.915250

Energy efficient signaling in deep submicron CMOS technology. / Dhaou, Imed Ben; Sundararajan, Vijay; Tenhunen, Hannu et al.
Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society, 2001. p. 319-324 915250 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dhaou, IB, Sundararajan, V, Tenhunen, H & Parhi, KK 2001, Energy efficient signaling in deep submicron CMOS technology. in Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001., 915250, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2001-January, IEEE Computer Society, pp. 319-324, 2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001, San Jose, United States, 3/26/01. https://doi.org/10.1109/ISQED.2001.915250

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abstract = "In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25pm, 2.5V, 6 metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.",

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AB - In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25pm, 2.5V, 6 metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.

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Energy efficient signaling in deep submicron CMOS technology

Abstract

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