Energy efficient signaling in deep submicron CMOS technology

Imed Ben Dhaou, Vijay Sundararajan, Hannu Tenhunen, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25pm, 2.5V, 6 metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001
PublisherIEEE Computer Society
Pages319-324
Number of pages6
ISBN (Electronic)0769510256
DOIs
StatePublished - Jan 1 2001
Event2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 - San Jose, United States
Duration: Mar 26 2001Mar 28 2001

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2001-January
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001
CountryUnited States
CitySan Jose
Period3/26/013/28/01

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