Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Jieming Yin; Pingqiang Zhou; Anup Holey; Sachin S. Sapatnekar; Antonia Zhai

doi:10.1145/2333660.2333675

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Jieming Yin
, Pingqiang Zhou
, Anup Holey
, Sachin S. Sapatnekar
, Antonia Zhai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

18 Scopus citations

Abstract

Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.

Original language	English (US)
Title of host publication	ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages	57-62
Number of pages	6
DOIs	https://doi.org/10.1145/2333660.2333675
State	Published - 2012
Event	2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States Duration: Jul 30 2012 → Aug 1 2012

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
Country/Territory	United States
City	Redondo Beach, CA
Period	7/30/12 → 8/1/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

frequency scaling
heterogeneous multi-core
interconnects
noc
non-minimal path routing
voltage scaling

Publisher link

10.1145/2333660.2333675

Find It

Find It at U of M Libraries

Cite this

Yin, J., Zhou, P., Holey, A., Sapatnekar, S. S., & Zhai, A. (2012). Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design (pp. 57-62). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/2333660.2333675

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. / Yin, Jieming; Zhou, Pingqiang; Holey, Anup et al.
ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. 2012. p. 57-62 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yin, J, Zhou, P, Holey, A, Sapatnekar, SS & Zhai, A 2012, Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. in ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 57-62, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, United States, 7/30/12. https://doi.org/10.1145/2333660.2333675

@inproceedings{b9b80d0cb3814f5582a6785b5b00ef25,

title = "Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems",

abstract = "Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.",

keywords = "frequency scaling, heterogeneous multi-core, interconnects, noc, non-minimal path routing, voltage scaling",

author = "Jieming Yin and Pingqiang Zhou and Anup Holey and Sapatnekar, \{Sachin S.\} and Antonia Zhai",

year = "2012",

doi = "10.1145/2333660.2333675",

language = "English (US)",

isbn = "9781450312493",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "57--62",

booktitle = "ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design",

note = "2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 ; Conference date: 30-07-2012 Through 01-08-2012",

}

TY - GEN

T1 - Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

AU - Yin, Jieming

AU - Zhou, Pingqiang

AU - Holey, Anup

AU - Sapatnekar, Sachin S.

AU - Zhai, Antonia

PY - 2012

Y1 - 2012

N2 - Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.

AB - Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.

KW - frequency scaling

KW - heterogeneous multi-core

KW - interconnects

KW - noc

KW - non-minimal path routing

KW - voltage scaling

UR - https://www.scopus.com/pages/publications/84865563005

UR - https://www.scopus.com/pages/publications/84865563005#tab=citedBy

U2 - 10.1145/2333660.2333675

DO - 10.1145/2333660.2333675

M3 - Conference contribution

AN - SCOPUS:84865563005

SN - 9781450312493

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 57

EP - 62

BT - ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design

T2 - 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12

Y2 - 30 July 2012 through 1 August 2012

ER -

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Abstract

Publication series

Other

UN SDGs

Keywords

Publisher link

Find It

Other files and links

Fingerprint

Cite this