Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S Sapatnekar, Antonia B Zhai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.

Original languageEnglish (US)
Title of host publicationISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages57-62
Number of pages6
DOIs
StatePublished - Sep 4 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: Jul 30 2012Aug 1 2012

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period7/30/128/1/12

Keywords

  • frequency scaling
  • heterogeneous multi-core
  • interconnects
  • noc
  • non-minimal path routing
  • voltage scaling

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