@inproceedings{b9b80d0cb3814f5582a6785b5b00ef25,
title = "Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems",
abstract = "Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve NoC energy and performance efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.",
keywords = "frequency scaling, heterogeneous multi-core, interconnects, noc, non-minimal path routing, voltage scaling",
author = "Jieming Yin and Pingqiang Zhou and Anup Holey and Sapatnekar, {Sachin S.} and Antonia Zhai",
year = "2012",
doi = "10.1145/2333660.2333675",
language = "English (US)",
isbn = "9781450312493",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "57--62",
booktitle = "ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design",
note = "2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 ; Conference date: 30-07-2012 Through 01-08-2012",
}