ML accelerators have largely focused on building general platforms for deep neural networks (DNNs), but less so on shallow machine learning (SML) algorithms. This paper proposes Axiline, a compact, configurable, template-based generator for SML hardware acceleration. Axiline identifies computational kernels as templates that are common to these algorithms and builds a pipelined accelerator for efficient execution. The dataflow graphs of individual ML instances, with different data dimensions, are mapped to the pipeline stages and then optimized by customized algorithms. The approach generates energy-efficient hardware for training and inference of various ML algorithms, as demonstrated with post-layout FPGA and ASIC results.
|Original language||English (US)|
|Title of host publication||2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - 2023|
|Event||2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Antwerp, Belgium|
Duration: Apr 17 2023 → Apr 19 2023
|Name||Proceedings -Design, Automation and Test in Europe, DATE|
|Conference||2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023|
|Period||4/17/23 → 4/19/23|
Bibliographical noteFunding Information:
This material is based on research sponsored in part by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650-20-2-7009. The U. S. government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of AFRL, DARPA, or the U. S. government.
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