Energy-efficient architectures for timing error-tolerant processors

John Sartori; Rakesh Kumar

doi:10.1109/ICEAC.2010.5702294

Energy-efficient architectures for timing error-tolerant processors

John Sartori
, Rakesh Kumar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.

Original language	English (US)
Title of host publication	2010 International Conference on Energy Aware Computing, ICEAC 2010
DOIs	https://doi.org/10.1109/ICEAC.2010.5702294
State	Published - Dec 1 2010
Event	2010 International Conference on Energy Aware Computing, ICEAC 2010 - Cairo, Egypt Duration: Dec 16 2010 → Dec 18 2010

Publication series

Name	2010 International Conference on Energy Aware Computing, ICEAC 2010

Other

Other	2010 International Conference on Energy Aware Computing, ICEAC 2010
Country/Territory	Egypt
City	Cairo
Period	12/16/10 → 12/18/10

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy
SDG 9 Industry, Innovation, and Infrastructure

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10.1109/ICEAC.2010.5702294

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Sartori, J & Kumar, R 2010, Energy-efficient architectures for timing error-tolerant processors. in 2010 International Conference on Energy Aware Computing, ICEAC 2010., 5702294, 2010 International Conference on Energy Aware Computing, ICEAC 2010, 2010 International Conference on Energy Aware Computing, ICEAC 2010, Cairo, Egypt, 12/16/10. https://doi.org/10.1109/ICEAC.2010.5702294

@inproceedings{cb1f76f61f7e46d8afc71ee028ab6886,

title = "Energy-efficient architectures for timing error-tolerant processors",

abstract = "Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.",

author = "John Sartori and Rakesh Kumar",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ICEAC.2010.5702294",

language = "English (US)",

isbn = "9781424482757",

series = "2010 International Conference on Energy Aware Computing, ICEAC 2010",

booktitle = "2010 International Conference on Energy Aware Computing, ICEAC 2010",

note = "2010 International Conference on Energy Aware Computing, ICEAC 2010 ; Conference date: 16-12-2010 Through 18-12-2010",

}

TY - GEN

T1 - Energy-efficient architectures for timing error-tolerant processors

AU - Sartori, John

AU - Kumar, Rakesh

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.

AB - Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.

UR - https://www.scopus.com/pages/publications/79952033087

UR - https://www.scopus.com/pages/publications/79952033087#tab=citedBy

U2 - 10.1109/ICEAC.2010.5702294

DO - 10.1109/ICEAC.2010.5702294

M3 - Conference contribution

AN - SCOPUS:79952033087

SN - 9781424482757

T3 - 2010 International Conference on Energy Aware Computing, ICEAC 2010

BT - 2010 International Conference on Energy Aware Computing, ICEAC 2010

T2 - 2010 International Conference on Energy Aware Computing, ICEAC 2010

Y2 - 16 December 2010 through 18 December 2010

ER -

Energy-efficient architectures for timing error-tolerant processors

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