Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights

Yunzhi Duan, Shuai Li, Ruipeng Zhang, Qi Wang, Jienan Chen, Gerald E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an energy-efficient, deep parallel Convolutional Neural Network (CNN) accelerator. By adopting a recently proposed binary weight method, the CNN computations are converted into multiplication-free processing. To allow parallel accessing and storing of data, we use two RAM banks, where each bank is composed of NRAM blocks corresponding to N-parallel processing. We also design a reconfigurable CNN computing unit in a divide-and-reuse to support a variable-size convolutional filter. Compared with full-precision computing on the MNIST and CIFAR-10 classification tasks, the inference Top-1 accuracy of the binary weight CNN has dropped by 1.21% and 1.34%, respectively. The hardware implementation results show that the proposed design can achieve 2100 GOPs with a 4.6 millisecond processing latency. The deep parallel accelerator exhibits 3X energy efficiency compared to a GPU-based design.

Original languageEnglish (US)
Title of host publication2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538668115
DOIs
StatePublished - Jan 31 2019
Event23rd IEEE International Conference on Digital Signal Processing, DSP 2018 - Shanghai, China
Duration: Nov 19 2018Nov 21 2018

Publication series

NameInternational Conference on Digital Signal Processing, DSP
Volume2018-November

Conference

Conference23rd IEEE International Conference on Digital Signal Processing, DSP 2018
CountryChina
CityShanghai
Period11/19/1811/21/18

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Keywords

  • Convolutional Neural Network (CNN)
  • deep neural network
  • energy efficiency
  • parallel implementation

Cite this

Duan, Y., Li, S., Zhang, R., Wang, Q., Chen, J., & Sobelman, G. E. (2019). Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights. In 2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018 [8631596] (International Conference on Digital Signal Processing, DSP; Vol. 2018-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICDSP.2018.8631596