TY - GEN
T1 - Enabling resonant clock distribution with scaled on-chip magnetic inductors
AU - Sinha, Saurabh
AU - Xu, Wei
AU - Velamala, Jyothi B.
AU - Dastagir, Tawab
AU - Bakkaloglu, Bertan
AU - Yu, Hongbin
AU - Cao, Yu
PY - 2009
Y1 - 2009
N2 - Resonant clock distribution with distributed LC oscillators is promising to reducing clock power and jitter noise. Yet the difficulty in the integration of on-chip inductors still limits its application in practice. This paper resolves such a key issue with sub-50 μm magnetic inductors, which are fully compatible with the CMOS process. These inductors leverage soft magnetic coils to achieve inductances up to 4nH, Q-factor of 3 at 1 GHz with a device diameter of only 30-50 μm, resulting in area savings of nearly 100X as compared to conventional design. The latency and noise performance of the resonant clock network is demonstrated to be comparable to those using conventional inductors without soft magnetic materials. In addition, inductors with integrated magnetic materials significantly reduce mutual coupling and eddy current loss in the power grid below the clock network. These design advantages enable high density of on-chip distributed oscillators, providing better phase averaging, lower power and superior noise characteristics as compared to traditional buffer-tree based clock network.
AB - Resonant clock distribution with distributed LC oscillators is promising to reducing clock power and jitter noise. Yet the difficulty in the integration of on-chip inductors still limits its application in practice. This paper resolves such a key issue with sub-50 μm magnetic inductors, which are fully compatible with the CMOS process. These inductors leverage soft magnetic coils to achieve inductances up to 4nH, Q-factor of 3 at 1 GHz with a device diameter of only 30-50 μm, resulting in area savings of nearly 100X as compared to conventional design. The latency and noise performance of the resonant clock network is demonstrated to be comparable to those using conventional inductors without soft magnetic materials. In addition, inductors with integrated magnetic materials significantly reduce mutual coupling and eddy current loss in the power grid below the clock network. These design advantages enable high density of on-chip distributed oscillators, providing better phase averaging, lower power and superior noise characteristics as compared to traditional buffer-tree based clock network.
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U2 - 10.1109/ICCD.2009.5413169
DO - 10.1109/ICCD.2009.5413169
M3 - Conference contribution
AN - SCOPUS:77950964143
SN - 9781424450282
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 103
EP - 108
BT - 2009 IEEE International Conference on Computer Design, ICCD 2009
T2 - 2009 IEEE International Conference on Computer Design, ICCD 2009
Y2 - 4 October 2009 through 7 October 2009
ER -