Enabling Effective Module-Oblivious Power Gating for Embedded Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John M Sartori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The increasingly-stringent power and energy requirements of emerging embedded applications have led to a strong recent interest in aggressive power gating techniques. Conventional techniques for aggressive power gating perform module-based power gating in processors, where power domains correspond to RTL modules. We observe that there can be significant power benefits from module-oblivious power gating, where power domains can include an arbitrary set of gates, possibly from multiple RTL modules. However, since it is not possible to infer the activity of module-oblivious power domains from software alone, conventional software-based power management techniques cannot be applied for module-oblivious power gating in processors. Also, since module-oblivious domains are not encapsulated with a well-defined port list and functionality like RTL modules, hardware-based management of module-oblivious domains is prohibitively expensive. In this paper, we present a technique for low-cost management of module-oblivious power domains in embedded processors. The technique involves symbolic simulation-based co-analysis of a processor's hardware design and a software binary to derive profitable and safe power gating decisions for a given set of module-oblivious domains when the software binary is run on the processor. Our technique is automated, does not require programmer intervention, and incurs low management overhead. We demonstrate that module-oblivious power gating based on our technique reduces leakage energy by 2x with respect to state-of-the-art aggressive module-based power gating for a common embedded processor.

Original languageEnglish (US)
Title of host publicationProceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017
PublisherIEEE Computer Society
Pages157-168
Number of pages12
ISBN (Electronic)9781509049851
DOIs
StatePublished - May 5 2017
Event23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017 - Austin, United States
Duration: Feb 4 2017Feb 8 2017

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017
CountryUnited States
CityAustin
Period2/4/172/8/17

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Keywords

  • Embedded
  • Leakage
  • Low-power
  • Power-gating

Cite this

Cherupalli, H., Duwe, H., Ye, W., Kumar, R., & Sartori, J. M. (2017). Enabling Effective Module-Oblivious Power Gating for Embedded Processors. In Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017 (pp. 157-168). [7920822] (Proceedings - International Symposium on High-Performance Computer Architecture). IEEE Computer Society. https://doi.org/10.1109/HPCA.2017.48