This paper presents an original methodology for layout-aware synthesis of analog systems. Layout parasitics (including capacitance, resistance and inductance) have a critical influence on system performances i.e. speed, bandwidth etc. We discuss the usage of layout templates during an exploration-based synthesis methodology that performs combined system parameter search, floorplanning and global routing. Predefined templates express the relative position of block and wires so that routing parasitics can be fastly extracted and considered during synthesis. The paper also presents the selection of the best layout template from a set of possible candidates. Two case studies are presented to exemplify the usage of layout templates for synthesis.
|Original language||English (US)|
|Title of host publication||Midwest Symposium on Circuits and Systems|
|State||Published - Dec 1 2002|
|Event||2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States|
Duration: Aug 4 2002 → Aug 7 2002
|Other||2002 45th Midwest Symposium on Circuits and Systems|
|Period||8/4/02 → 8/7/02|