Elliptic curve scalar multiplier design using FPGAs

Lijun Gao, Sarvesh Shrivastava, Gerald E Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

A compact fast elliptic curve scalar multiplier with variable key size is implemented as a coprocessor with a Xilinx FPGA. This implementation utilizes the internal SRAM/registers of the FPGA and has the whole scalar multiplier implemented within a single FPGA chip. The compact design helps reduce the overhead and limitations associated with data transfer between FPGA and host, and thus leads to high performance. The experimental data from the mappings over small fields shows that the carefully constructed hardware architecture is regular and has high CLB utilization.

Original languageEnglish (US)
Title of host publicationCryptographic Hardware and Embedded Systems - 1st International Workshop, CHES 1999, Proceedings
EditorsCetin K. Koc, Paar Paar
PublisherSpringer Verlag
Pages257-268
Number of pages12
ISBN (Print)354066646X, 9783540666462
DOIs
StatePublished - 1999
Event1st Workshop on Cryptographic Hardware and Embedded Systems, CHES 1999 - Worcester, United States
Duration: Aug 12 1999Aug 13 1999

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1717
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other1st Workshop on Cryptographic Hardware and Embedded Systems, CHES 1999
CountryUnited States
CityWorcester
Period8/12/998/13/99

Keywords

  • Coprocessor
  • Elliptic curves
  • FPGA
  • Galois field
  • Public-key cryptography
  • Reconfigurable hardware
  • Scalar multiplication

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