Eliminating the fanout bottleneck in parallel long BCH encoders

Research output: Chapter in Book/Report/Conference proceedingConference contribution

42 Scopus citations

Abstract

Long BCH codes can achieve about 0.6-dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.

Original languageEnglish (US)
Title of host publicationIEEE Transactions on Circuits and Systems I: Regular Papers
Pages512-516
Number of pages5
Volume51
DOIs
StatePublished - Mar 2004

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