Eliminating the fanout bottleneck in parallel long BCH encoders

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Long BCH codes can achieve about 0.6dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.

Original languageEnglish (US)
Pages (from-to)2611-2615
Number of pages5
JournalIEEE International Conference on Communications
StatePublished - 2004
Event2004 IEEE International Conference on Communications - Paris, France
Duration: Jun 20 2004Jun 24 2004


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