Electron and hole mobility enhancement in strained SOI by wafer bonding

Lijuan Huang, Jack O. Chu, S. A. Goma, C. P. D'Emic, Steven J. Koester, Donald F. Canaperi, Patricia M. Mooney, S. A. Cordes, James L. Speidell, R. M. Anderson, H. S.Philip Wong

Research output: Contribution to journalArticlepeer-review

62 Scopus citations

Abstract

N-and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates.

Original languageEnglish (US)
Pages (from-to)1566-1571
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume49
Issue number9
DOIs
StatePublished - Sep 2002

Bibliographical note

Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.

Keywords

  • CMOS
  • Mobility
  • SiGe
  • Silicon-on-insulator (SOI)
  • Strained silicon
  • Wafer bending

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