Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip

Nakul Pande; C. Zhou; M. H. Lin; R. Fung; R. Wong; S. Wen; C. H. Kim

Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip

Nakul Pande, C. Zhou, M. H. Lin, R. Fung, R. Wong, S. Wen, C. H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.

Original language	English (US)
Title of host publication	2021 Symposium on VLSI Technology, VLSI Technology 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487802
State	Published - 2021
Event	41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan Duration: Jun 13 2021 → Jun 19 2021

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2021-June
ISSN (Print)	0743-1562

Conference

Conference	41st Symposium on VLSI Technology, VLSI Technology 2021
Country/Territory	Japan
City	Virtual, Online
Period	6/13/21 → 6/19/21

Bibliographical note

Funding Information:
The data collection and analysis work was supported in part by Semiconductor Research Corporation (SRC).

Publisher Copyright:
© 2021 JSAP

Keywords

Bit-Error-Rate
Circuit reliability
Datapath
Electromigration
Signal-interconnects

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Pande, N., Zhou, C., Lin, M. H., Fung, R., Wong, R., Wen, S., & Kim, C. H. (2021). Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip. In 2021 Symposium on VLSI Technology, VLSI Technology 2021 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc..

Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip. / Pande, Nakul; Zhou, C.; Lin, M. H. et al.
2021 Symposium on VLSI Technology, VLSI Technology 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Pande, N, Zhou, C, Lin, MH, Fung, R, Wong, R, Wen, S & Kim, CH 2021, Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip. in 2021 Symposium on VLSI Technology, VLSI Technology 2021. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 41st Symposium on VLSI Technology, VLSI Technology 2021, Virtual, Online, Japan, 6/13/21.

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abstract = "An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.",

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AU - Wong, R.

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AB - An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.

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Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip

Abstract

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