An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.
|Original language||English (US)|
|Title of host publication||2021 Symposium on VLSI Technology, VLSI Technology 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - 2021|
|Event||41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan|
Duration: Jun 13 2021 → Jun 19 2021
|Name||Digest of Technical Papers - Symposium on VLSI Technology|
|Conference||41st Symposium on VLSI Technology, VLSI Technology 2021|
|Period||6/13/21 → 6/19/21|
Bibliographical noteFunding Information:
The data collection and analysis work was supported in part by Semiconductor Research Corporation (SRC).
© 2021 JSAP
- Circuit reliability