Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points

Chen Zhou, Richard Wong, Shi Jie Wen, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A 65nm test chip to study electromigration (EM) effects in power grids was taped-out and tested. A 9×9 grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the die temperature to 350°C without damaging the chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could observe for the first time, subtle behaviors of EM such as mechanical stress dependent failure locations and self-healing due to redundant current paths.

Original languageEnglish (US)
Title of host publication2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages19-20
Number of pages2
ISBN (Electronic)9781538642160
DOIs
StatePublished - Oct 25 2018
Event38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
Duration: Jun 18 2018Jun 22 2018

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2018-June
ISSN (Print)0743-1562

Other

Other38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/TerritoryUnited States
CityHonolulu
Period6/18/186/22/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

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