A 65nm test chip to study electromigration (EM) effects in power grids was taped-out and tested. A 9×9 grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the die temperature to 350°C without damaging the chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could observe for the first time, subtle behaviors of EM such as mechanical stress dependent failure locations and self-healing due to redundant current paths.
|Original language||English (US)|
|Title of host publication||2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|State||Published - Oct 25 2018|
|Event||38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States|
Duration: Jun 18 2018 → Jun 22 2018
|Name||Digest of Technical Papers - Symposium on VLSI Technology|
|Other||38th IEEE Symposium on VLSI Technology, VLSI Technology 2018|
|Period||6/18/18 → 6/22/18|
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