Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points

Chen Zhou; Richard Wong; Shi Jie Wen; Chris H. Kim

doi:10.1109/VLSIT.2018.8510638

Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points

Chen Zhou, Richard Wong, Shi Jie Wen, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

A 65nm test chip to study electromigration (EM) effects in power grids was taped-out and tested. A 9×9 grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the die temperature to 350°C without damaging the chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could observe for the first time, subtle behaviors of EM such as mechanical stress dependent failure locations and self-healing due to redundant current paths.

Original language	English (US)
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	19-20
Number of pages	2
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510638
State	Published - Oct 25 2018
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: Jun 18 2018 → Jun 22 2018

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Other

Other	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	6/18/18 → 6/22/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Publisher link

10.1109/VLSIT.2018.8510638

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Zhou, C., Wong, R., Wen, S. J., & Kim, C. H. (2018). Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 19-20). Article 8510638 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510638

Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points. / Zhou, Chen; Wong, Richard; Wen, Shi Jie et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 19-20 8510638 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhou, C, Wong, R, Wen, SJ & Kim, CH 2018, Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510638, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 19-20, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 6/18/18. https://doi.org/10.1109/VLSIT.2018.8510638

Zhou C, Wong R, Wen SJ, Kim CH. Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 19-20. 8510638. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2018.8510638

Zhou, Chen ; Wong, Richard ; Wen, Shi Jie et al. / Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points. 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 19-20 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "A 65nm test chip to study electromigration (EM) effects in power grids was taped-out and tested. A 9×9 grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the die temperature to 350°C without damaging the chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could observe for the first time, subtle behaviors of EM such as mechanical stress dependent failure locations and self-healing due to redundant current paths.",

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Electromigration effects in power grids characterized using an on-chip test structure with poly heaters and voltage tapping points

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