Electromigration (EM) is seen as a growing problem in recent and upcoming technology nodes, and affects a wider variety of wires (e.g., power grid, clock/signal nets), circuits (e.g., digital, analog, mixed-signal), and systems (e.g., mobile, server, automotive), touching lower levels of metal than before. Moreover, unlike traditional EM checks that were performed on each wire individually, EM checks must evolve to consider the system-level impact of wire failure. This requires a change in how interconnect design incorporates this effect. This paper overviews the root causes of EM, its impact on high-performance designs, and techniques for analyzing, working around, and alleviating the effects of EM.
|Original language||English (US)|
|Title of host publication||ISPD 2019 - Proceedings of the 2019 International Symposium on Physical Design|
|Publisher||Association for Computing Machinery|
|Number of pages||8|
|State||Published - Apr 4 2019|
|Event||2019 ACM International Symposium on Physical Design, ISPD 2019 - San Francisco, United States|
Duration: Apr 14 2019 → Apr 17 2019
|Name||Proceedings of the International Symposium on Physical Design|
|Conference||2019 ACM International Symposium on Physical Design, ISPD 2019|
|Period||4/14/19 → 4/17/19|
Bibliographical noteFunding Information:
This work was supported in part by the NSF under awards CCF-1421606, CCF-1714805, and by the DARPA IDEA program. The author gratefully acknowledges the work of Dr. Vivek Mishra, Dr. Palkesh Jain, and Vidya Chhabria that led to many of the insights in this paper.
© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.
- Clock networks
- Power grids