In developing a simulator for a new processor architecture, it often is not clear whether it is more efficient to write a new simulator or to modify an existing simulator. Writing a new simulator forces the processor architect to develop or adapt all of the related software tools. However, modifying an existing simulator and related tools, which are usually not well-documented, can be time-consuming and error-prone. We describe the SImulator for Multithreaded Computer Architectures (SIMCA) that was developed with the primary goal of obtaining a functional simulator as quickly as possible to begin evaluating the superthreaded architecture. The performance of the simulator itself was important, but secondary. We achieved our goal using a technique called process-pipelining that exploits the unique features of this new architecture to hide the details of the underlying simulator. This approach allowed us to quickly produce a functional simulator whose performance is only 3.8-4.9 times slower than the base simulator.
|Original language||English (US)|
|Number of pages||7|
|State||Published - Jan 1 1998|
|Event||Proceedings of the 1998 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems, MASCOTS - Montreal, Can|
Duration: Jul 19 1998 → Jul 24 1998
|Other||Proceedings of the 1998 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems, MASCOTS|
|Period||7/19/98 → 7/24/98|