Abstract
In this article, the authors present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.
Original language | English (US) |
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Article number | 6762794 |
Pages (from-to) | 120-137 |
Number of pages | 18 |
Journal | IEEE Micro |
Volume | 34 |
Issue number | 3 |
DOIs | |
State | Published - 2014 |
Keywords
- hardware
- high performance computing
- networking
- processing element
- spatial parallelism
- triggered instruction