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Efficient power based Galois Field arithmetic architectures
Surendra K. Jain,
Keshab K. Parhi
Electrical and Computer Engineering
Research output
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Contribution to conference
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Paper
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peer-review
1
Scopus citations
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Keyphrases
Efficient Power
100%
New Architecture
100%
Galois Field Arithmetic
100%
Cryptography
50%
VLSI Systems
50%
Exponentiation
50%
Error Control Coding
50%
Concurrency
50%
Pattern Matching
50%
Galois Field
50%
Divider
50%
Speed-power
50%
Simple Control
50%
Low-power Implementation
50%
General Operation
50%
Computer Science
Power Efficient
100%
Critical Path
100%
Clock Cycle
50%
Pattern Matching
50%
Concurrency
50%
Error Control Coding
50%
Interconnection Pattern
50%
Divider
50%
Computer Hardware
50%
Engineering
Critical Path
100%
Pattern Matching
50%
Clock Cycle
50%