Efficient power based Galois Field arithmetic architectures

Surendra K. Jain, Keshab K. Parhi

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

Galois Field has been used for numerous applications including error control coding and cryptography. The design of efficient multipliers, dividers and exponentiation circuits for Galois Field Arithmetic is needed for these applications. Recently, an approach based on Pattern Matching was developed which can yield a throughput of 1 result every clock cycle. We suggest an improvement to the existing design to reduce the hardware and critical path. This reduction in the critical path can lead to a higher speed or lower power implementation depending on the application. We also propose a new architecture to perform a general operation like ABn+C. The new architecture is more efficient than the present schemes. The architecture presented has simple control, regular and local interconnection pattern and complete concurrency in operations and is therefore well suited for VLSI systems.

Original languageEnglish (US)
Pages306-315
Number of pages10
StatePublished - Dec 1 1994
EventProceedings of the 1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
Duration: Oct 26 1994Oct 28 1994

Other

OtherProceedings of the 1994 IEEE International Workshop VLSI Signal Processing
CityLa Jolla, CA, USA
Period10/26/9410/28/94

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    Jain, S. K., & Parhi, K. K. (1994). Efficient power based Galois Field arithmetic architectures. 306-315. Paper presented at Proceedings of the 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA, .