Efficient PEEC-based inductance extraction using circuit-aware techniques

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circuit characteristics to define the concept of resistance-dominant and inductance-dominant lines. This notion is used to progressively refine a set of clusters that are inductively tightly-coupled. For reasonable designs, the more exact Algorithm 1 yields a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, while the more approximate Algorithm 2 achieves up to 99% sparsification. An offshoot of this work is K-PRIMA, an extension of PRIMA to handle K matrices with guaranteed passivity.

Original languageEnglish (US)
Pages434-439
Number of pages6
StatePublished - Jan 1 2002
EventInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors - Freiburg, Germany
Duration: Sep 16 2002Sep 18 2002

Other

OtherInternational Conference on Computer Design (ICCD'02) VLSI in Copmuters and Processors
Country/TerritoryGermany
CityFreiburg
Period9/16/029/18/02

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