Efficient parallel VLSI architecture for linear feedback shift registers

Manohar Ayinala, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Linear feedback shift register (LFSR) is an important part of the cyclic redundancy check (CRC) operations and BCH encoders. This paper presents a novel high speed parallel LFSR architecture based on parallel Infinite Impulse Response (IIR) filter design, pipelining and retiming algorithms. A new formulation is proposed to modify the LFSR into the form of an IIR filter. Then pipelining and retiming algorithms are applied to further reduce the critical path in the parallel architecture. A comparison between the proposed and previous architectures shows that our parallel architecture achieves a critical path same as that of previous designs with a reduced hardware cost.

Original languageEnglish (US)
Title of host publication2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
Pages52-57
Number of pages6
DOIs
StatePublished - Dec 27 2010
Event2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - San Francisco, CA, United States
Duration: Oct 6 2010Oct 8 2010

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Country/TerritoryUnited States
CitySan Francisco, CA
Period10/6/1010/8/10

Keywords

  • Cyclic redundancy check (CRC)
  • Linear feedback shift register (LFSR)
  • Look-ahead computation
  • Parallel processing
  • Pipelining

Fingerprint

Dive into the research topics of 'Efficient parallel VLSI architecture for linear feedback shift registers'. Together they form a unique fingerprint.

Cite this