Efficient minarea retiming of large level-clocked circuits

Naresh Maheshwari, Sachin S. Sapatnekar

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations

Abstract

Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).

Original languageEnglish (US)
Article number655956
Pages (from-to)840-845
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - Dec 1 1998
EventDesign, Automation and Test in Europe, DATE 1998 - Paris, France
Duration: Feb 23 1998Feb 26 1998

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