Efficient inductance extraction using circuit-aware techniques

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We propose two practical approaches for on-chip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous methods in that they use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resistance-dominant and inductance-dominant lines. Specifically, they begin by finding inductance-dominant lines and forming initial clusters, followed by heuristically enlarging and/or combining these clusters, with the goal of including only the important inductance terms in the sparsifted K matrix. Algorithm 1 permits the influence of the magnetic field of aggressor lines to reach the edge of the chip, while Algorithm 2 works under the simplified assumptions that the supply lines have zero ∑j Lij (dIj/dt) drops (but have nonzero parasitic Rs and Cs) and that currents cannot return through supply lines beyond a user-defined distance. For reasonable designs, Algorithm 1 delivers a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, as compared to Algorithm 2 where the sparsification can reach 99% for the same delay error. An offshoot of this work is the development of K-PRIMA, an extension of the reduced-order modeling technique, PRIMA, to handle K matrices with guarantees of passivity.

Original languageEnglish (US)
Pages (from-to)746-761
Number of pages16
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number6
StatePublished - Dec 2002

Bibliographical note

Funding Information:
Manuscript received December 12, 2001; revised June 15, 2002. This work was supported in part by the SRC by Grant 99-TJ-714 and by the NSF by Award CCR-0098117. H. Hu was with the Department of ECE, University of Minnesota, Minneapolis, MN 55455 USA. She is now with the Motorola Inc., Austin, TX 78729 USA (e-mail: hhu@mail.ece.umn.edu; Haitian.Hu@motorola.com). S. Sapatnekar is with the Department of ECE, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: sachin@mail.ece.umn.edu). Digital Object Identifier 10.1109/TVLSI.2002.808455


  • Circuit analysis
  • Circuit simulation
  • Extraction
  • Inductance
  • Interconnect
  • Magnetic interaction
  • Model-order reduction


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