Efficient In-Memory Processing Using Spintronics

Zamshed I Chowdhury, Jonathan D. Harms, S. Karen Khatamifard, Masoud Zabihi, Yang Lv, Andrew P. Lyle, Sachin S Sapatnekar, Ulya Karpuzcu, Jianping Wang

Research output: Contribution to journalArticlepeer-review

42 Scopus citations


As the overhead of data retrieval becomes forbidding, bringing processor logic to the memory where the data reside becomes more energy-efficient. While traditional CMOS structures are unsuited to the tight integration of logic and memory, emerging spintronic technologies show remarkable versatility. This paper introduces a novel spintronics-based processing-in-memory (PIM) framework called computational RAM (CRAM) to solve data-intensive computing problems.

Original languageEnglish (US)
Pages (from-to)42-46
Number of pages5
JournalIEEE Computer Architecture Letters
Issue number1
StatePublished - Jan 1 2018

Bibliographical note

Funding Information:
This work is supported by DARPA Non-Volatile Logic program, NSF SPX grant no. 1725420, and by C-SPIN, one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. Chowdhury and Harms equally contributed to this work.

Publisher Copyright:
© 2017 IEEE.


  • CRAM
  • MTJ
  • processing-in-memory
  • spintronics


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