Efficient highly-parallel decoder architecture for quasi-cyclic low-density parity-check codes

Daesun Oh, Keshab K Parhi

Research output: Contribution to journalConference articlepeer-review

15 Scopus citations

Abstract

In this paper, we propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction In hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.

Original languageEnglish (US)
Article number4253023
Pages (from-to)1855-1858
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Sep 27 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: May 27 2007May 30 2007

Fingerprint

Dive into the research topics of 'Efficient highly-parallel decoder architecture for quasi-cyclic low-density parity-check codes'. Together they form a unique fingerprint.

Cite this