Efficient high-speed quasi-cyclic LDPC decoder architecture

Yuping Zhang, Zhongfeng Wang, Keshab K Parhi

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

This paper studies load imbalance problem in the two stages of belief propagation decoding algorithm for LDPC codes and re-distributes computational load between two stages. To further reduce the critical path delay, new look-up-tables (LUT) are developed to replace both conventional LUTs and data format transformation blocks. The adder trees are also reorganized for speed. This novel approach can reduce the critical path delay by 41.0% with negligible increase in the logic core size. This paper also exploits the similarity between these two stages and derives an area efficient design that re-maps the functional units for these two stages onto the same hardware, which can reduce the logic core size by 10.2% and reduce the critical path delay by 16.2%.

Original languageEnglish (US)
Pages (from-to)540-544
Number of pages5
JournalConference Record - Asilomar Conference on Signals, Systems and Computers
Volume1
StatePublished - Dec 1 2004
EventConference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Nov 7 2004Nov 10 2004

Fingerprint Dive into the research topics of 'Efficient high-speed quasi-cyclic LDPC decoder architecture'. Together they form a unique fingerprint.

Cite this