Efficient folded VLSI architectures for linear prediction error filters

Sayed Ahmad Salehi, Rasoul Amirfattahi, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this paper we propose two efficient low-area, low-power folded VLSI architectures for linear prediction error filter. One of them is based on the split-Levinson-Durbin and requires half computational complexity of an architecture based on the Levinson-Durbin algorithm. The other one is based on the Schur algorithm. Using folding method, the number of multipliers and adders is minimized. In addition, by modifications in data scheduling, the number of required multiplexers are also decreased. Comparison with previous architectures demonstrates the efficiency of the proposed architectures with respect to hardware and computational complexity.

Original languageEnglish (US)
Title of host publicationGLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012
Pages357-362
Number of pages6
DOIs
StatePublished - May 22 2012
Event22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT, United States
Duration: May 3 2012May 4 2012

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
CountryUnited States
CitySalt Lake City, UT
Period5/3/125/4/12

Keywords

  • Folding transformation
  • Levinson-durbin
  • Low-power
  • Schur
  • Split-levinson
  • VLSI

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    Salehi, S. A., Amirfattahi, R., & Parhi, K. K. (2012). Efficient folded VLSI architectures for linear prediction error filters. In GLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012 (pp. 357-362). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/2206781.2206867