In this paper we propose two efficient low-area, low-power folded VLSI architectures for linear prediction error filter. One of them is based on the split-Levinson-Durbin and requires half computational complexity of an architecture based on the Levinson-Durbin algorithm. The other one is based on the Schur algorithm. Using folding method, the number of multipliers and adders is minimized. In addition, by modifications in data scheduling, the number of required multiplexers are also decreased. Comparison with previous architectures demonstrates the efficiency of the proposed architectures with respect to hardware and computational complexity.