This paper presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - Dec 1 1999|
|Event||1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan|
Duration: Oct 20 1999 → Oct 22 1999