Efficient FFT implementation using digit-serial arithmetic

Yun Nan Chang; Keshab K. Parhi

Efficient FFT implementation using digit-serial arithmetic

Yun Nan Chang, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

This paper presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

Original language	English (US)
Pages (from-to)	645-653
Number of pages	9
Journal	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
State	Published - Dec 1 1999
Event	1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan Duration: Oct 20 1999 → Oct 22 1999

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title = "Efficient FFT implementation using digit-serial arithmetic",

abstract = "This paper presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.",

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AU - Chang, Yun Nan

AU - Parhi, Keshab K.

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N2 - This paper presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

AB - This paper presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

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M3 - Conference article

AN - SCOPUS:0033342032

SN - 1520-6130

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JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

T2 - 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation'

Y2 - 20 October 1999 through 22 October 1999

ER -

Efficient FFT implementation using digit-serial arithmetic

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