Efficient FFT implementation using digit-serial arithmetic

Yun Nan Chang, Keshab K. Parhi

Research output: Contribution to journalConference article

13 Scopus citations

Abstract

This paper presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By splitting the sequential input sample into parallel digit-serial data streams, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

Original languageEnglish (US)
Pages (from-to)645-653
Number of pages9
JournalIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
StatePublished - Dec 1 1999
Event1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan
Duration: Oct 20 1999Oct 22 1999

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