A novel connection between digit-serial computation and skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our approach, a digit size of N bits is mapped onto an N-phase overlapping clocking scheme in such a way that N bits are processed in each full clock cycle. In addition, a VHDL-based verification strategy is used to capture the essential time-borrowing behavior of skew-tolerant domino circuits in an accurate and efficient manner. The simulation results show that an 8-tap digit-serial FIR filter constructed with skew-tolerant domino is up to 36% faster than one built using traditional domino circuits.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2002|