Efficient and scalable cross-ISA virtualization of hardware transactional memory

Wenwen Wang; Pen Chung Yew; Antonia Zhai; Stephen McCamant

doi:10.1145/3368826.3377919

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Wenwen Wang, Pen Chung Yew, Antonia Zhai, Stephen McCamant

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

System virtualization is a key enabling technology. However, existing virtualization techniques suffer from a significant limitation due to their limited cross-ISA support for emerging architecture-specific hardware extensions. To address this issue, we make the first attempt at hardware transactional memory (HTM), which has been supported by modern multi-core processors and used by more and more applications to simplify concurrent programming. In particular, we propose an efficient and scalable mechanism to support cross- ISA virtualization of HTMs. The mechanism emulates guest HTMs using host HTMs, and tries to preserve as much as possible the performance and the scalability of guest applications. Experimental results on STAMP benchmarks show that an average of 2.3X and 12.6X performance speedup can be achieved respectively for x86-64 and PowerPC64 guest applications on an x86-64 host machine. Moreover, it can attain similar scalability to the native execution of the applications.

Original language	English (US)
Title of host publication	CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization
Editors	Jason Mars, Lingjia Tang, Jingling Xue, Peng Wu
Publisher	Association for Computing Machinery, Inc
Pages	107-120
Number of pages	14
ISBN (Electronic)	9781450370479
DOIs	https://doi.org/10.1145/3368826.3377919
State	Published - Feb 22 2020
Event	18th ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2020 - San Diego, United States Duration: Feb 22 2020 → Feb 26 2020

Publication series

Name	CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization

Conference

Conference	18th ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2020
Country/Territory	United States
City	San Diego
Period	2/22/20 → 2/26/20

Bibliographical note

Publisher Copyright:
© 2020 Copyright held by the owner/author(s).

Keywords

Cross-ISA
DBT
HTM
System Virtualization

Publisher link

10.1145/3368826.3377919

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Wang, W., Yew, P. C., Zhai, A., & McCamant, S. (2020). Efficient and scalable cross-ISA virtualization of hardware transactional memory. In J. Mars, L. Tang, J. Xue, & P. Wu (Eds.), CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization (pp. 107-120). (CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization). Association for Computing Machinery, Inc. https://doi.org/10.1145/3368826.3377919

Efficient and scalable cross-ISA virtualization of hardware transactional memory. / Wang, Wenwen; Yew, Pen Chung ; Zhai, Antonia et al.
CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization. ed. / Jason Mars; Lingjia Tang; Jingling Xue; Peng Wu. Association for Computing Machinery, Inc, 2020. p. 107-120 (CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, W, Yew, PC , Zhai, A & McCamant, S 2020, Efficient and scalable cross-ISA virtualization of hardware transactional memory. in J Mars, L Tang, J Xue & P Wu (eds), CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization. CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization, Association for Computing Machinery, Inc, pp. 107-120, 18th ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2020, San Diego, United States, 2/22/20. https://doi.org/10.1145/3368826.3377919

Wang W, Yew PC , Zhai A , McCamant S. Efficient and scalable cross-ISA virtualization of hardware transactional memory. In Mars J, Tang L, Xue J, Wu P, editors, CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization. Association for Computing Machinery, Inc. 2020. p. 107-120. (CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization). doi: 10.1145/3368826.3377919

Wang, Wenwen ; Yew, Pen Chung ; Zhai, Antonia et al. / Efficient and scalable cross-ISA virtualization of hardware transactional memory. CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization. editor / Jason Mars ; Lingjia Tang ; Jingling Xue ; Peng Wu. Association for Computing Machinery, Inc, 2020. pp. 107-120 (CGO 2020 - Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization).

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AB - System virtualization is a key enabling technology. However, existing virtualization techniques suffer from a significant limitation due to their limited cross-ISA support for emerging architecture-specific hardware extensions. To address this issue, we make the first attempt at hardware transactional memory (HTM), which has been supported by modern multi-core processors and used by more and more applications to simplify concurrent programming. In particular, we propose an efficient and scalable mechanism to support cross- ISA virtualization of HTMs. The mechanism emulates guest HTMs using host HTMs, and tries to preserve as much as possible the performance and the scalability of guest applications. Experimental results on STAMP benchmarks show that an average of 2.3X and 12.6X performance speedup can be achieved respectively for x86-64 and PowerPC64 guest applications on an x86-64 host machine. Moreover, it can attain similar scalability to the native execution of the applications.

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Efficient and scalable cross-ISA virtualization of hardware transactional memory

Abstract

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Keywords

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