Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET's

Chris H. Kim, Hari Ananthan, Jae Joon Kim, Kaushik Roy

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

A study, which demonstrated that Ground Plane (GP)-SOI devices are optimal for the digital body biasing (DBB) technique, was presented. GP SOI MOSFET was shown to have advantages over bulk devices, such as better controllability of V t, and the absence of p-n junctions, which alleviates the issues related to forward-biased junction currents for swapped back biases. It was shown that GP-SOI MOSFET's were optimal for the DBB scheme offering high on-current and low design complexity without having power/performance issues related to the forward-biased p-n junction current in bulk CMOS. The result also shows that GP-SOI can deliver same performance as DG-SOI at 90X lower standby leakage by dynamically switching the back-gate bias.

Original languageEnglish (US)
Article numberP5.2
Pages (from-to)69-70
Number of pages2
JournalProceedings - IEEE International SOI Conference
StatePublished - Dec 1 2004
Event2004 IEEE International SOI Conference, Proceedings - Charleston, SC, United States
Duration: Oct 4 2004Oct 7 2004

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