Modern applications for DSP systems are increasingly constrained by tight area and power requirements. Therefore, it is imperative to analyze effective strategies that work within these requirements. This paper studies the impact of finite word-length arithmetic on the signal to quantization noise ratio (SQNR), power and area for a real-valued serial FFT implementation. An experiment is set up using a hardware description language (HDL) to empirically determine the tradeoffs associated with the following parameters: (i) the input word-length, (ii) the word-length of the rotation coefficients, and (iii) length of the FFT on performance (SQNR), power and area. The results of this paper can be used to make design decisions by careful selection of word-length to achieve a reduction in area and power for an acceptable loss in SQNR.
|Original language||English (US)|
|Title of host publication||2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - 2019|
|Event||2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan|
Duration: May 26 2019 → May 29 2019
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019|
|Period||5/26/19 → 5/29/19|
Bibliographical noteFunding Information:
This research was supported in part by the National Science Foundation under grant number CCF-1814759.
- Real-valued FFT
- Serial commutator