The ion implantation steps used in fabricating field effect transistors in ultrathin (6 to 30 nm) silicon-on-insulator (UTSOI) substrates present many challenges. Deep source/drain (S/D) implants in UTSOI layers are a particular concern, since it can be difficult to implant the desired dose without amorphizing the entire SOI thickness. In a first study, we investigated the effect of implant temperature (20 to 300 °C) on the sheet resistance (Rs) of 28 nm thick SOI layers implanted with As+ at an energy of 50 keV and a dose of 3 × 1015 /cm2, and found Rs values after activation sharply lower for samples implanted at the highest temperature. In a second study, on 8 nm thick SOI layers implanted with As+ at an energy of 0.75 keV and doses in the range 0.5 to 2 × 1015 /cm5, the benefits of the elevated implantation temperature were less clear. Explanations for these effects, supported by microscopy, medium energy ion scattering (MEIS), and optical reflectance data, will be discussed.