Early-stage power grid analysis for uncertain working modes

Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar

Research output: Contribution to journalArticle

20 Scopus citations

Abstract

High-performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact integer linear programming (ILP) method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43 K nodes is analyzed within 70 s, and the worst-case scenarios found correlate well with the results from an ILP solver.

Original languageEnglish (US)
Pages (from-to)676-682
Number of pages7
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume24
Issue number5
DOIs
StatePublished - May 1 2005

Keywords

  • Early-stage simulation
  • Power grid
  • Random walk
  • Supply network

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