Abstract
High-performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact integer linear programming (ILP) method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43 K nodes is analyzed within 70 s, and the worst-case scenarios found correlate well with the results from an ILP solver.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 676-682 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 24 |
| Issue number | 5 |
| DOIs | |
| State | Published - May 2005 |
Bibliographical note
Funding Information:Manuscript received June 1, 2004; revised September 7, 2004. This work was supported in part by the Semiconductor Research Corporation under Contract 2003-TJ-1092, in part by the National Science Foundation under Award CCR-0205227, and in part by an IBM Faculty Award. This paper was recommended by Guest Editor P. Groeneveld.
Keywords
- Early-stage simulation
- Power grid
- Random walk
- Supply network