Early-stage power grid analysis for uncertain working modes

Haifeng Qian, Sani R. Nassif, Sachin S Sapatnekar

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations


High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact ILP method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43K nodes is analyzed within 70 seconds, and the worst-case scenarios found correlate well with the results from an ILP solver.

Original languageEnglish (US)
Number of pages6
StatePublished - 2004
EventProceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, United States
Duration: Apr 18 2004Apr 21 2004


OtherProceedings of the International Symposium on Physical Design, ISPD 2004
Country/TerritoryUnited States
CityPhoenix, AZ


  • Early estimation
  • Power grid
  • Random walk
  • Supply network


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