Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors

Chris H. Kim, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Scopus citations

Abstract

This paper presents a Dynamic Vt SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The Vt of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high Vt only when it is not likely to be accessed anymore. Simulation results from SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
Pages251-254
Number of pages4
StatePublished - Dec 1 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period8/12/028/14/02

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